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Digital VLSI Design with Verilog

This hands-on course presents to the students the design of digital integrated circuits using the Verilog digital design language as described in IEEE Standard 1364-2005. Using a balanced mixture of lecture and lab, the students are introduced to language constructs in a progressively more complex project environment. The entire Verilog language is covered.

During the course, students will become familiar with the use of the Synopsys Design Compiler to synthesize gate-level netlists from behavioral, RTL, and structural Verilog code. The synthesis constraints most useful for area and speed optimization are emphasized. A large fraction of the lab work is done in the synthesizable subset of the language; logic simulation is treated as an occasional verification method. Other topics include design partitioning, hierarchy decomposition, safe coding styles, back-annotation, assertion-based verification, and design for test. The class project is a full-duplex serializer-deserializer.

Class/Lab Duration and Hours

This is a 12-week course which meets three times a week, twice for combined lecture and lab (3 hours each), and once for dedicated lab (4 hours). The dedicated lab may be split into two 2-hour meetings. Days and times are fixed at the first meeting; typically, sessions begin at 6 PM on weekday evenings.

REGISTER

For additional information about this class and other classes, including the course outline, schedule, tuition, etc. please send email to info@svtii.com or call 408-573-0100. Group discounts are available for groups of 3 or more.

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