HOME

Design for Testability Fundamentals

This class is targeted to engineers or managers who want learn basics of DFT techniques and theory. Basic DFT techniques and their application will be taught in this class.

Contents:

• What is testing, VLSI, Fault Models, Levels of Abstraction
• Testability Analysis, Test Approaches – Ad Hoc and Structured
• Scan Cell Design, Scan Architecture, Scan Design Rules, Scan Design Flow
• Simulation Introduction, Logic Simulation Models, Logic Optimization, Fault Simulation Models
• Test Generation Methods, Exhaustive Test Generation, Combinational Circuit Testing and models, ATPG (automatic test pattern generation), Stuck-At Fault testing, IDDQ Testing
• BIST (built-in self-testing), Pseudo-Exhaustive/Random Testing, Logic BIST Architecture,
• Test Compression Techniques
• Memory Testing and BIST
• Analog and Mixed Signal Testing

Prerequisite: Basic knowledge of electrical and computer engineering, or computer science.

Duration: 12 weeks, 2 sessions per week

Tuition fee for the course include: 

• 12 weeks of instruction and hands-on work

• Certificate

REGISTER

For additional information about this class and other classes, including the schedule, tuition, etc. please send email to info@svtii.com or call 408-573-0100.